In some digital displays such as televisions, data must be transmitted within the display panel, e.g., display data may be transmitted from a timing controller on a printed circuit board (PCB) behind the display panel to driver integrated circuits (ICs) on the display panel. In such an implementation, each driver IC requires a clock signal, i.e., a receiver clock, which may also be referred to as a sampling clock, to sample the received data.
A sampling clock may be extracted, by the driver IC, from the transitions embedded in the data sequence, a process that may require a clock and data recovery circuit (CDR) at the receiver, and a form of transition encoding on the transmitted data, to insure that transitions in the received data are sufficiently frequent. In another kind of implementation, the driver ICs receive a low-frequency clock from the transmitter, and use a phase-locked loop (PLL) to multiply the clock frequency to the required rate for sampling the received data.
Transmitter clock jitter may result in irregularity in the timing of transitions in the transmitted data. It may also result in irregularity in the timing of edges in the transmitted clock, if a clock is transmitted. In CDR-based or PLL-based receivers, due to inherent low-pass filtering in the CDR or PLL, the correlation between high-frequency clock jitter and data jitter may be significantly reduced. This may result in changes in timing margin, as illustrated in FIG. 1A, in which timing margin is defined as the time interval between a clock edge and the subsequent transition in the received data. Such changes in timing margin may limit the maximum data rates achievable with acceptably low error rates. If, on the other hand, the receiver clock jitter were fully correlated with the received data's jitter, the effects of timing jitter would be cancelled.
An intra-panel interface, e.g., the interface between a timing controller (TCON) and driver ICs in a display may be asymmetric in the sense that the receivers, i.e., the driver ICs, are noisy, because they include high-voltage display column drivers, and the driver ICs are slow, because they are fabricated in a high-voltage process, while the transmitter, i.e., the TCON, is fabricated in a standard process with standard voltages, and is therefore quieter and faster. As a result it is desirable to place precision circuitry in the transmitter rather than in the receiver, when possible.
Thus, there is a need for a system and method for providing a clock signal to several receivers which preserves the correlation between clock jitter and data jitter, and which is implemented primarily in the transmitter.